Date created: Thursday, December 24, 2015 9:11:13 AM. Last modified: Thursday, August 13, 2020 5:56:34 PM

ASR1000 Hardware Overview


At the start of 2016 the ESP 5G & 10G, RP1, SIP 10G, ASR1001 and ASR1002 are becoming EoS and ultimately EoL.

Initial product range: List of ASR1000 series Embedded Services Processors: 2.5-Gbps, 5-Gbps, 10-Gbps, 10-Gbps Non Crypto, 20-Gbps, 40-Gbps, 100-Gbps and 200-Gbps



Example chassis: ASR1009-X

SPA Interface Processors: 3 SIP/MIP/fixed Ethernet card slots per chassis
Shared port adapters: upto 12 SPAs (up to 4 per SIP depending on SPA size)
SIPs supported: 40-Gbps SIP Carrier Card (ASR1000-SIP40)

Modular Ethernet Cards: 3 SIP/MIP/fixed Ethernet card slots per chassis
Modular cards supported: MIP 100-Gbps Carrier Card (ASR1000-MIP100)
Ethernet Port Adapters: 6 EPA slots (two per MIP card)
EPAs supported: 1x100GE QSFP Ethernet Port Adapter (EPA-QSFP-1X100GE), 1x100GE Ethernet Port Adapter (EPA-1X100GE), 2x40GE Ethernet Port Adapter Native QSFP (EPA-2X40GE), 2x40GE Ethernet Port Adapter Native QSFP with 1 port disabled (EPA-1X40GE), 2x40GE Ethernet Port Adapter - breakout cable (EPA-CPAK-2X40GE), 10x10GE Ethernet Port Adapter (EPA-10X10GE), 18x1GE Ethernet Port Adapter (EPA-18X1GE)

Fixed Ethernet Cards: 3 SIP/MIP/fixed Ethernet card slots per chassis
Fixed Ethernet line cards supported: 2x 10 GE + 20x 1 GE (ASR1000-2T+20X1GE), 6x 10 GE (ASR1000-6TGE)

Route Processor Slows: 2 route-processor slots
RSPs Supported: RP2, RP3

Series ESP Slots: 2 ESP slots (these are the fabric cards)
ESPs Supported: 40-Gbps ESP (ASR1000-ESP40), 100-Gbps ESP (ASR1000-ESP100), and 200-Gbps ESP (ASR1000-ESP200)
ESP Bandwidth: 40 to 200 Gbps

Embedded hardware-based encryption: Yes - On 40-Gbps ESP (ASR1000-ESP40) with up to 11-Gbps crypto throughput, 100-Gbps ESP (ASR1000-ESP100) with up to 29-
Gbps crypto throughput, and 200-Gbps ESP (ASR1000-ESP200) with up to 78-Gbps crypto throughput.



Example RSP: RP3

Chassis support: ASR 1006-X, 1009-X, and 1013 chassis

Memory options: 8-GB memory default; upgradable to 16-GB, 32-GB, or 64-GB memory

Storage options: 100-GB SSD (hot-swappable); upgradable to 200-GB or 400-GB SSD, and 1-GB USB compact flash memory

Route Scale:
With 8-GB memory:
 - Up to 1,000,000 IPv4 routes or 1,000,000 IPv6 routes
 - BGP RR scalability up to 8,000,000 IPv4 routes or 6,000,000 IPv6 routes
With 16-GB memory:
 - Up to 4,000,000 IPv4 routes or 4,000,000 IPv6 routes
 - BGP RR scalability up to 24,000,000 IPv4 routes or 17,000,000 IPv6 routes
With 32-GB memory:
 - Up to 8,500,000 IPv4 routes or 7,500,000 IPv6 routes
 - BGP RR scalability up to 24,000,000 IPv4 routes or 17,000,000 IPv6 routes



Example: ESP200

"ASR 1000 Series Embedded Services Processors (ESPs) handle all the network data-plane traffic‑processing tasks of Cisco ASR 1000 Series Aggregation Services Routers. These ESPs allow the activation of concurrent enhanced network services, such as cryptography, firewall, Network Address Translation (NAT), quality of service (QoS), NetFlow, and many others while maintaining line speeds."

Up to 152 Mpps - Variable forwarding performance, depending on features configured

Normal Forwarding: Up to 200 Gbps -  For the combination of commonly used features + Firewall or NAT, shared by all Cisco ASR 1000 SIP (ASR1000-SIP40) cards
Encryption: Up to 78 Gbps - For plain IPsec encryption (1400-byte packets), for GETVPN, more than one GDOI group

Access control: Up to 4,000 unique ACLs and 400,000 ACEs per system
Broadband: Up to 58,000 sessions and 16,000 L2TP tunnels
IP: Up to 4,000,000 IPv4 or 4,000,000 IPv6 routes
Multicast: 100,000 routes and 44,000 groups

Flexible number of queues per system
Up to 464,000 queues
Three levels of hierarchy
Two LLQ queues per policy, with up to 4,000 policies
8-kbps policing and queuing granularity
<100-microsecond latency for high-priority applications

Real-time traffic:  Up to 4,000 CRTP sessions

Security, Up to:
IPsec: 8000 tunnels
Firewall: 6,000,000 sessions and 220,000 sessions-per-sec setup rate
NAT: 4,000,000 sessions and 300,000 sessions-per-sec setup rate
Carrier-Grade NAT: 12,000,000 sessions

L3VPN: Up to 8,000 VRF instances

GRE: Up to 4,000 tunnels

Cisco Unified Border Element (SP Edition):
Up to 64,000 sessions (each session represents a complete voice call with 14 SIP messages per call; that is, two call legs on the SBC consisting of two media legs for a bidirectional media flow and seven SIP messages per call leg)


Fixed Ethernet Cards, Modular Interface Cards and Ethernet Port Adapters

Example fixed Ethernet line card: ASR1000-6TGE

The ASR1000-6TGE card is a fixed-port Ethernet line card. This line card has six 10-GE (XFP) ports. This line card is capable of 60-Gbps of input traffic and 40-Gbps of output traffic forwarding using a fixed-port interface design. The ASR1000-2T+20X1GE  card is capable of 40Gbps of dull-duplex forwarding.

Example modular interface card: ASR1000-MIP100

The Cisco ASR 1000 Series Modular Interface Processor (ASR1000-MIP100) is a full-duplex 100-Gbps modular Ethernet line card that is capable of hosting up to two Cisco ASR 1000 Series Ethernet Port Adapters (EPAs). The card can be installed in any of the slots (0/1/2) in the ASR1009-x chassis. The ASR1000-MIP100 architecture is composed of a host carrier card, which accepts two EPAs. Each EPA can support either one 100 GE port or ten 10 GE ports. Overall, the ASR1000-MIP100 line card can support either two 100 GE ports, or twenty 10 GE ports, or one 100 GE port + ten 10 GE ports. The MIP100 capable of 100 Gbps full-duplex traffic forwarding towards the ESP fabric. With two 1x100GE EPAs the MIP100 will be 2:1 oversubscribed on the backplane.

Example Ethernet port adapter: EPA-QSFP-1X100GE

EPAs are small plug-in modules containing circuitry to provide optical or electrical network interfaces. The packet data between the EPA and MIP carrier card can support a 100Gbps full-duplex bandwidth. The data path supports operating at various predefined data rates and protocols.


Cisco's QFP

ESPs are powered by the (QFP) Quantum Flow Processor complex which is two ASICs (a traffic processing ASIC and buffering/queueing ASIC) working together.

Higher speed ESPs simple have more QFP chips than a lower speed ESPs. The more recent ESPs also use a newer generation of QFP. Lower speed ESPs possibly also have some cores disabled? For example, an ESP2.5 has 10 cores and an ESP5 has 20 cores (are half the cores are disabled on the ESP2.5?). Each Cisco ASR 1000-ESP200 uses 4x 3rd generation Cisco QFPs to provide 256 cores.

The 1st generation of QFP codenamed “Popeye” is based on 40 cores (Tensilica ISA) supporting 160 processes, running at 400Mhz, with 128MB DRAM for packet memory, 512MB DRAM for resources, SRAM (20MBs?) and 10Mb TCAM for forwarding lookups and packet operations. These are 32bit RISC processors. Each Popeye or PPE ASIC cluster feeds into the Traffic Manager ASIC or BQS ASIC (Buffer, Queue, Schedule) codenamed “Spinach”.

The TCAM is used for: Class/Policy Maps: QoS, DPI, FW, ACL/ACE storage, IPSec Security Association class groups, classes, rules, and NAT tables.
The Resource DRAM is used for: QoS Mark/Police, NAT sessions, IPSec SAs, Netflow Cache, FW hash tables, Per session data (FW, NAT, Netflow, SBC).
The Packet Buffer DRAM is used for: QoS Queuing, NAT VFR re-assembly, IPSec headers.

The 2nd generation of QFP codenamed “Luke”? has 62 or 64 cores and supports 256 traffic processing threads.

The 3rd generation of QFP codenamed “Yoda” supports 64 core and up to 256 traffic processing threads, up to four of these can be meshed to provide 256 cores 1024 traffic processing threads Each QFP ASIC complex can process 70Gbps or 32Mpps. These use 80Mb TCAM, 2GBs of resource DRAM for packet processing operations and look-ups and 512MB of DRAM for packet buffering.

The output of the command “show platform hardware qfp active infrastructure exmem statistics” shows DRAM, IRAM and SRAM:
DRAM == 1GB PPE RLDRAM2 (RDRAM or Resource DRAM) for NAT sessions, NetFlow cache, Firewall sessions, hash tables, IPSec SA, QoS markings and policing.
IRAM == 128MB instruction RAM used for QFP code (FIA array), can also store data
SRAM == 32KB used for high speed traffic management functions e.g. virtual reassembly

ASR1002, ESP5, ESP10 & ESP20 use the CPP10 ASIC (40 cores)
ESP40 use the CPP10+ ASIC (40 cores)
ESP80 uses 2x QFPs – not sure which generation – was this ever released it was marketed in 2010?
ESP100 use 2x Yoda ASICs
ESP200 uses 4x Yoda ASICs
ASR1002-X uses 1x Yoda ASIC
ASR1001-X uses 1x Luke ASIC
ISR4400 uses Octeon processor
ISR4300 uses it’s RP cores

With an ESP200 for example; 4x Yoda QFPs are used providing (4x2GBs) 8GBs of packet processing memory, (4x512MBs) 2GBs of packet buffering memory, but only two TCAMs are used providing (2x80Mb) 160Mb of TCAM.